september 2006 advance information copyright ? alliance memory. all rights reserved. AS7C1026C 5 v 64k x 16 cmos sram 12/5/06, v 1.0 alliance memory p. 1 of 9 ? features ? industrial (-40 o to 85 o c) temperature ? organization: 65,536 words 16 bits ? center power and ground pins for low noise ? high speed - 12 ns address access time - 6 ns output enable access time ? low power consumption via chip deselect ? easy memory expansion with ce , oe inputs ? ttl-compatible, three-state i/o ? upper and lower byte pin ? jedec standard packaging - 44-pin 400 mil soj - 44-pin tsop 2-400 ? esd protection 2000 volts logic block diagram 65,536 x 16 array oe ce we address decoder address decoder a0 a1 a2 a3 a4 a5 a7 v cc gnd a8 a9 a10 a11 a12 a13 a14 a15 control circuit i/o0?i/o7 i/o8?i/o15 ub lb i/o buffer a6 pin arrangement 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o13 i/o12 gnd v cc i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 nc a0 ce i/o0 i/o1 i/o2 i/o3 v cc gnd i/o4 i/o5 i/o6 i/o7 we a15 a14 a13 44-pin soj (400 mil), tsop 2 21 22 a12 nc ub lb i/o15 i/o14 2 a3 3 a2 4 a1 1 a4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a6 a7 oe a5 AS7C1026C
AS7C1026C 12/5/06, v 1.0 alliance memory p. 2 of 9 ? functional description the AS7C1026C is a 5v high-performance cmos 1,048,576-b it static random access memory (sram) device organized as 65,536 words 16 bits. it is designed for memory applications wh ere fast data access, low po wer, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 12 ns with output enable access times (t oe ) of 6 ns are ideal for high- performance applications. when ce is high, the device enters standby mode. if inputs are still toggling, the device will consume i sb power. if the bus is static, then full standb y power is reached (i sb1 ). a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o0 through i/o15 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ) with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input addr ess. when either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. the device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o0 through i/o7, and ub controls the higher bits, i/o8 through i/o15. all chip inputs and outputs are ttl-compatible, and operation is from a single 5 v supply. the AS7C1026C is packaged in common industry stan dard packages. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outsid e those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. key: h = high, l = low, x = don?t care. absolute maximum ratings parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.50 +7.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc +0.50 v power dissipation p d ?1.25w storage temperature (plastic) t stg ?55 +125 c ambient temperature with vcc applied t bias ?55 +125 c dc current into outputs (low) i out ?50ma truth table ce we oe lb ub i/o0?i/o7 i/o8?i/o15 mode hxxxxhigh zhigh z standby (i sb ), i sbi ) lhllhd out high z read i/o0?i/o7 (i cc ) lhlhlhigh zd out read i/o8?i/o15 (i cc) lhllld out d out read i/o0?i/o15 (i cc ) llxll d in d in write i/o0?i/o15 (i cc ) llxlh d in high z write i/o0?i/o7 (i cc ) llxhlhigh zd in write i/o8?i/o15 (i cc ) l l h x h x x h x h high z high z output disable (i cc )
AS7C1026C 12/5/06, v 1.0 alliance memory p. 3 of 9 ? recommended operating conditions notes: v il min = -1.5v for pulse width less than 5ns, once per cycle. v ih max = v cc +2.0v for pulse width less than 5ns, once per cycle. parameter symbol min nominal max unit supply voltage v cc 4.5 5.0 5.5 v input voltage v ih 2.2 ? v cc + 0.5 v v il ?0.5 ? 0.8 v ambient operating temperature (industrial) t a ?40 ? 85 o c dc operating characteristics (over the operating range) 1 parameter sym test conditions AS7C1026C-12 unit min max input leakage current | i li | v cc = max, v in = gnd to v cc ?5a output leakage current | i lo | v cc = max, ce = v ih , v out = gnd to v cc ?5a operating power supply current i cc v cc = max, ce v il , i out = 0ma, f = f max ? 210 ma standby power supply current i sb v cc = max, ce v ih , f = f max ?60ma i sb1 v cc = max, ce v cc ?0.2 v, v in 0.2 v or v in v cc ?0.2 v, f = 0 ?10ma output voltage v ol i ol = 8 ma, v cc = min ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? v capacitance (f = 1mhz, t a = 25 c, v cc = nominal) 2 parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe , lb , ub v in = 0 v 6 pf i/o capacitance c i/o i/o v out = 0 v 7 pf note: this parameter is guaranteed by device ch aracterization, but is not production tested.
AS7C1026C 12/5/06, v 1.0 alliance memory p. 4 of 9 ? key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (oe , ce , ub , lb controlled) 3,6,8,9 read cycle (over the operating range) 3,9 parameter symbol AS7C1026C-12 unit notes min max read cycle time t rc 12 ? ns address access time t aa ?12ns3 chip enable (ce ) access time t ace ?12ns3 output enable (oe ) access time t oe ?7ns output hold from address change t oh 4?ns5 ce low to output in low z t clz 4 ? ns 4, 5 ce high to output in high z t chz ? 6 ns 4, 5 oe low to output in low z t olz 0 ? ns 4, 5 byte select access time t ba ?7ns byte select low to low z t blz 0 ? ns 4, 5 byte select high to high z t bhz ? 6 ns 4, 5 oe high to output in high z t ohz ? 6 ns 4, 5 power up time t pu 0 ? ns 4, 5 power down time t pd ?12ns4, 5 undefined output/don?t care falling input rising input t oh t aa t rc t oh data out address data valid previous data valid data valid t rc t aa t blz t ba t oe t olz t oh t ohz t hz t bhz t ace t lz address oe ce lb , ub data in
AS7C1026C 12/5/06, v 1.0 alliance memory p. 5 of 9 ? write waveform 1 (we controlled) 11 write cycle (over the operating range) 11 parameter symbol AS7C1026C-12 unit notes min max write cycle time t wc 12 ? ns chip enable (ce ) to write end t cw 9?ns address setup to write end t aw 9?ns address setup time t as 0?ns write pulse width t wp 9?ns write recovery time t wr 0?ns address hold from end of write t ah 0?ns data valid to write end t dw 7?ns data hold time t dh 0?ns5 write enable to output in high z t wz ? 6 ns 4, 5 output active from write end t ow 1 ? ns 4, 5 byte select low to end of write t bw 9?ns address ce lb , ub we data in data out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t wr data undefined high z data valid t ah
AS7C1026C 12/5/06, v 1.0 alliance memory p. 6 of 9 ? write waveform 2 (ce controlled) 11 ac test conditions notes: 1 during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a and b. 4 these parameters are specified with c l = 5 pf, as in figures b. transition is measured 200 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address is valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 n/a. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 not applicable. 13 c = 30 pf, except all high z and low z parameters where c = 5 pf. address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t ow t wz t wr data out data undefined high z high z t as t aw data valid t clz t ah 168 thevenin equivalent: d out +1.728 v 255 c 13 480 gnd +5 v figure b: 5 v output load 10% 90% 10% 90% gnd +3.0v figure a: input pulse 3 ns d out ? output load: see figure b. ? input pulse level: gnd to 3.0 v. see figure a. ? input rise and fall times: 3 ns. see figure a. ? input and output timing reference levels: 1.5
AS7C1026C 12/5/06, v 1.0 alliance memory p. 7 of 9 ? package dimensions 44-pin tsop 2 min (mm) max (mm) a 1.2 a1 0.05 0.15 a2 0.95 1.05 b 0.30 0.45 c 0.120 0.21 d 18.31 18.52 e 10.06 10.26 he 11.68 11.94 e 0.80 (typical) l 0.40 0.60 d he 1234567891011121314 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 1718 19 20 28 27 26 25 c l a1 a2 e 44-pin tsop 2 0?5 21 24 22 23 e a b seating plane 44-pin soj 44-pin soj 400 mil min (in) max (in) a 0.128 0.148 a 1 0.025 ? a 2 0.105 0.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.120 1.130 e 0.370 nom e 1 0.395 0.405 e 2 0.435 0.445 e 0.050 nom e pin 1 a 1 b b a a 2 e 2 e 1 d c e
AS7C1026C 12/5/06, v 1.0 alliance memory p. 8 of 9 ? ordering codes package volt/ temp 12 ns plastic soj, 400 mil 5v industrial AS7C1026C-12jin tsop 2, 10.2 x 18.4 mm 5v industrial AS7C1026C-12tin part numbering system as7c 1026c ?xx x x x sram prefix device number access time package: j = soj 400 mil t = tsop 2, 10.2 x 18.4 mm temperature range: i = industrial: -40 c to 85 c n = lead free part
alliance memory, inc. 1116 south amphlett san mateo, ca 94402 tel: 650-525-3737 fax: 650-525-0449 www.alliancememory.com copyright ? alliance memory all rights reserved part number: AS7C1026C document version: v 1.0 ? copyright 2003 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or re gistered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make chan ges to this document and its products at any time without noti ce. alliance assumes no responsibility for any errors that may appear in this document. the da ta contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at an y time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in thi s product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any gua rantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product desc ribed herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and condi tions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of s ale. the purchase of products from alliance does not convey a license under any patent rights , copyrights; mask works rights, trademarks, or any other intell ectual property rights of alliance or third parties. alliance does not authorize its produc ts for use as critical components in life-supporting systems w here a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-support ing systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. AS7C1026C ? ?
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